1. Field of the Invention
The present invention relates to a recording apparatus for improving a recording speed of recording data onto an optical disc, an encoding device and an encoding method applied to the recording apparatus, and a scrambler circuit suitably applicable to the encoding device.
2. Description of Related Art
Following so-called 1st generation optical discs such as CD, CD-R/RW and CD-ROM and 2nd generation optical discs such as Digital Versatile Disc (DVD), so-called 3rd generation optical disc that is Blu-ray discs with a shorter light source wavelength of 405 nm (blue-violet light) has been developed. The Blu-ray discs allows reading and writing record marks at a recording density of about five times that of DVD by increasing the numerical aperture (NA) of an objective lens to 0.85 to reduce a beam spot area to about one-fifth that of DVD in addition to shortening a light source wavelength. Further, Blu-ray discs have a phase change recording layer that is covered with a transparent covering layer of 0.1 mm thick and placed on a disc substrate, thereby reducing aberration due to the relative inclination of a disc and laser light (cf. “Next generation optical disc” Nikkei Electronics Books, Oct. 7, 2003).
The data structure of a Blu-ray disc is specified as follows by the standard. FIG. 20 is a view to describe the data structure of a Blu-ray disc. In the Blu-ray standard, recording data is recorded onto a disc 301 in units of recording unit block (RUB) 302, which is referred to herein also as the cluster. The RUB 302 is made up of run-in 303 and run-out 305 that are a buffer field or a gap field for data overwrite, and a physical cluster 304 that is placed between these fields. The run-in 303 is composed of 2760 channel bits (cbs) and the run-out 305 is composed of 1104 cbs. The physical cluster is composed of 1932 cbs*496 frames=958272 cbs. The run-in 303 and the run-out 305 add up to a channel bit length of two frames or recording frames, which are described later. The physical cluster 304 is composed of burst indicator subcode (BIS) that contains user data, disc address information and so on.
The physical cluster 304 is composed of 496 recording frames 306. A frame sync is placed in the beginning of each recording frame 306. Thus, 498 frames which are a sum of the 496 frames (recording frames 306) that constitute the physical cluster 304 and the 2 frames of the run-in 303 and the run-out 305 form 1 RUB 302.
The recording frame 306 is composed of 1932 cbs and modulated by 1-7 PP (parity preserve/prohibit RMTR) code. It is then demodulated and Digital sum value (DSV) control (decontrol) bit is deleted from the demodulated data, thereby creating an ECC cluster.
FIG. 21 is a diagram showing an ECC cluster. An ECC cluster 401 is made up of 496 frames, which includes user data 402, ECC parity 404 and BIS 403. The extraction of the user data 402 and the EC parity 404 forms a long distance code (LDC) cluster, and 64 frames of the 496 frames form the ECC parity 404. The extraction of the BIS 403 forms a BIS cluster.
The BIS cluster contains address information of a disc. The address information (9 bytes) of the BIS cluster is allocated to each address unit having 31 frames, which is formed by dividing the ECC cluster of 496 frames into 16 segments. The BIS is composed of 9 bytes with 3 frames, which is 3 bytes per frame, address is contained in the first 4 bytes. Thus, obtaining the first 2 frames in each address unit allows obtaining address information (address unit number) of each address unit. The BIS cluster changes into the format called the BIS block when it is deinterleaved. The LDC cluster also changes into the format called the LDC block when it is deinterleaved.
FIG. 22 is a diagram showing an LDC block 501. The LDC block is created by deinterleaving the data which is obtained by extracting the user data 402 and the ECC parity 404 from the ECC cluster shown in FIG. 21 and which has 152 bytes in the horizontal direction (one frame) and 496 frames in the vertical direction. The deinterleaving process is performed in two stages. Firstly, the process increases a shift amount by 3 bytes every 2 frames and makes rotation in the right direction on the drawing. The process then inserts each byte of an even number frame between each byte of an odd number frame, thereby creating the data having 304 bytes, which is double the data before the deinterleaving, in the horizontal direction (one frame) and 248 frames, which is half, in the vertical direction.
In FIG. 22, the part of the LDC block 501 other than the ECC parity 503 is data block 502. One data block is composed of 32 sectors from Sec 0 to Sec 31. One sector has 2052 bytes, which includes 2048 bytes of the user data 504 and 4 bytes of error detecting code (EDC) 505. If the direction of data recording sequence is a recording frame direction P and the direction as user data is a user data direction Q, the recording frame direction P is in the horizontal direction (row direction) on the drawing and the user data direction Q is in the vertical direction (column direction) on the drawing. Thus, the data recording sequence and the user data sequence are different.
One sector has user data sequences, each sequence having 216 bytes, that are arranged in the user data direction Q in folded configuration. Thus, in the user data 504, each sequence (216 bytes) is arranged in the recording frame direction P. One sector Sec of 2052 bytes therefore has nine and half sequences in the user data direction Q. Since the EDC 505 of 4 bytes is placed at the end of the user data 504 of 2048 bytes in each sector Sec, if a sector number of the first sector is 0 (Sec 0), the EDC 505 in an even number sector is placed at the middle of one sequence in the user data direction Q.
FIG. 23 is a view showing an encoding order of each data for generating RUB from user data and address information. An LDC cluster and a BIS cluster are generated separately. An LDC cluster D6 is generated as follows. Firstly, Step SP1 adds EDC to user data D1 to create data frame D2. The addition of EDC is performed for each sector Sec and a sector of 2052 bytes added with EDC is obtained by performing a predetermined operation on a sector having the user data of 2048 bytes and 0 data of 4 bytes sequentially in the user data direction Q.
Then, Step SP 2 performs scrambling on EDC added data (data frame) D2 to which EDC has been added to create scrambled data (scrambled data frame) D3. The scrambling performs a predetermined arithmetical operation on data of one sector having 2052 bytes which is added with EDC in the user data direction Q. After that, Step SP3 rearranges the rows and columns of the scrambled data D3 to create a data block D4. Then, Step SP4 adds ECC parity to the data block D4 to create an LDC block D5. Finally, Step SP5 performs the interleaving as described above on the LDC block D5, thereby creating an LDC cluster D6.
On the other hand, a BIS cluster D11 is generated as follows. Firstly, Step SP6 interleaves user control data D8 and Step SP7 adds ECC to an address unit number D7 and interleaves the data to create an access block D9 from these data. Then, Step SP8 adds BIS ECC to the access block D9 to create a BIS block D10. Finally, Step SP9 interleaves the BIS block D10, thereby creating a BIS cluster D11.
After that, Step SP10 combines the LDC cluster D6 and the BIS cluster D11 to create an ECC cluster D12. Step SP11 adds a synchronization signal (frame sync) and a DSV control bit to the ECC cluster D12 to create a physical cluster D13. Then, Step SP12 adds run-in and run-out to the physical cluster D13 and performs 17PP modulation, thereby creating RUB D14 that contains 495 recording frames D143 together with run-in D141 and run-out D142 that are placed at the beginning and end of the recording frames.
FIG. 24 is a diagram showing a scrambler circuit for performing scrambling in Step SP2. The 32 bits from PS0 to PS31 shown in FIG. 24 indicate physical sector numbers. The physical sector number is a physical address for a sector of data 2 KB and has 4 bytes (32 bits). Upon reading and writing with 1 cluster of 64 KB constituting 1 RUB, 32 physical sector numbers are allocated to one cluster. Of the 32 bits physical sector numbers, 15 bits from PS5 to PS19 are cluster numbers (cluster address CN in units of RUB).
The scrambler circuit 601 includes a shift register 602 of 16 bits according to the multinomial below and XOR circuits 603 to 605.Φ(x)=X16+X15+X13+X4+1
S0 to S15 indicate the data retained in the shift register 602, which is referred to herein as the 16-bit shift register value. The shift register 602 shifts the value of data Sj to S(j+1) where j=0 to 14 each clock of a shift clock CKs. When scrambling, at the beginning of data block (RUB) to be scrambled, data S0 to S15 is loaded to the shift register 602 according to the parallel load signal PL. In this case, as data S0 to S14, the values of PS5 to PS19 in the physical sector number are loaded and preset as scrambling initial values in each sector. The physical sector number that is preset in this manner is the first physical sector number in the cluster. A fixed value “1” is loaded as a scrambling initial value of data S15.
In this way, as data S0 to S15 of the shift register 602, the cluster number in the physical sector number is preset as a scrambling initial value. At this time, the first low order 8 bits S0 to S7 serve as a first scrambling byte, which is referred to herein as the scramble value.
The shift register 602 outputs the low-order 8 bits of the 16-bit shift register value that has been shifted by 8 bits from the scrambling initial value by the shift clock as a scramble value (Sk) in synchronization with the timing to make 1-byte input (Dk) in the user data direction Q. Scrambled data D′k that is the data after scrambling the user data is calculated by exclusive OR operation of the input data Dk and the scramble value Sk output at Dk input timing.D′k=Dk xor Sk (k=0, 1, . . . 2051)where xor represents exclusive OR operation.
The scrambling obtains the scrambled data D′k from the scramble value Sk that is obtained by the shift register 602 and the data Dk of 2052 bytes in the user data direction Q that constitutes the sector Sec shown in FIG. 22.
A reproducing apparatus for Blu-ray disc that is formatted as described above is disclosed in Japanese Unexamined Patent Application Publication No. 2004-192749. FIG. 25 is a block diagram showing a conventional reproducing apparatus described therein. A disc 701 is driven to rotate at constant linear velocity (CLV) by a spindle motor 752 during recording and reproducing operation. Then, an optical pickup (optical head) 751 carries out the recording or reproduction of data on the disc 701.
The pickup 751 has a laser diode that serves as a laser light source, a photo-detector for detecting reflected light, and an objective lend that serves as an output end of laser light to create an optical system that applies laser light to a disc recording surface through the objective lens and guides reflected light to the photo-detector, through not shown. The pickup 751 is movable in the disc radius direction by a thread mechanism 753. The laser diode outputs blue laser with the wavelength of 405 nm. The NA of the optical system is 0.85 and the laser emission is controlled by a drive signal (drive current) from a laser driver 763. The reflected light information from the disc 701 is detected by the photo-detector and changed into an electrical signal according to detected light intensity, and then supplied to a matrix circuit 754.
The matrix circuit 754 has a current-voltage converter and a matrix operating/amplifying circuit corresponding to the output current from a plurality of photo-receiving devices as the photo-detector and generates a necessary signal by matrix operation. For example, it generates a high-frequency signal corresponding to reproduction data (reproduction data signal), a focus error signal for servo control, a tracking error signal, a push-pull signal related to wobbling groove and so on.
The reproduction data signal that is output from the matrix circuit 754 is supplied to a reader/writer circuit (RW circuit) 755, the focus error signal and the tracking error signal are supplied to a servo circuit 761, and the push-pull signal indicating detection information of wobbling groove is supplied to a wobble circuit 758.
The push-pull signal related to wobbling groove that is output from the matrix circuit 754 when the disc 701 is a rewritable disc is processed by the wobble circuit 758. The wobble circuit 758 performs MSK demodulation and HMW demodulation on the push-pull signal indicating ADIP information so as to demodulate the signal into data stream constituting ADIP address and supplies the data stream to an address decoder 759. The address decoder 759 generates a clock by PLL processing using the wobble signal supplied from the wobble circuit 758, and supplies it to each component as an encode clock for recording, for example.
In the recording, recording data is transferred from an AV system 720 and sent to memory in an ECC/scrambling circuit 757 for buffering. In this case, the ECC/scrambling circuit 757 performs processing such as addition of an error correction code, scrambling and addition of sub-code to encode the buffered recorded data. ECC encoding and ECC decoding are the process correspond to ECC format which uses reed Solomon (RS) code with RS (248, 216, 33), code length 248, data 216, and distance 33. The data after ECC encoding and scrambling is then modulated in RLL(1-7)PP system by a modulation/demodulation circuit 756 and supplied to the reader/writer circuit 755. An encode clock that serves as a reference clock for the encoding process during recording is a clock generated from the wobble signal described above.
The reader/writer circuit 755 performs recording compensation processing such as fine adjustment of an optimum recording power for the characteristics of a recording layer, the spot shape of laser light, a recording linear velocity and so on and adjustment of a laser drive pulse waveform on the recording data that is generated by the encoding process. The recording data is then sent to the laser driver 763 as a laser drive pulse. The laser driver 763 applies the laser drive pulse to the laser diode in the pickup 751 to drive the laser emission. The pit (phase change mark) corresponding to the recording data is thereby formed on the disc 701.
A spindle servo circuit 762 controls a spindle motor 752 to make CLV rotation. The spindle servo 762 acquires the clock generated by PLL processing for a wobble signal as present rotational speed information of the spindle motor 752 and compares it with predetermined CLV reference speed information, thereby creating a spindle error signal.
The operations of the servo system and the recording and reproducing system as described above are controlled by a system controller 760 that is configured by a micro computer. The system controller 760 performs various operations according to a command from the AV system 720. For example, if the AV system 720 outputs a write command, the system controller 760 first moves the pickup 751 to an address to which data is to be written. Then, the system controller 760 controls the ECC/scrambling circuit 757 and the modulation/demodulation circuit 756 so as to perform the encoding processing as described above on the data transferred from the AV system 720, which is video data of various formats such as MPEG2 and audio data, for example. Then, a laser drive pulse from the reader/writer circuit 755 is supplied to the laser driver 763, thereby conducting recording. In the recording or reproducing of the data, the system controller 260 controls access or recording and reproducing operation by using the ADIP address detected by the address decoder 759 or the address contained in BIS.
The above technique, which is disclosed in Japanese Unexamined Patent Application Publication 2004-192749, aims at providing ROM medium or the like that has superior RAM compatibility and takes advantages in tracking servo by scrambling the linking data (run-in and run-out) of Blu-ray disc with the same process as the main data (user data).
Referring back to FIG. 22, the EDC 505 that is added to each sector is obtained by performing a predetermined operation on each sector sequentially in the user data direction Q. Further, the scrambling circuit 601 shown in FIG. 24 outputs scramble value Sk for the sequence in the user data direction Q for each sector of 2052 bytes added with EDC. Thus, in the scrambling processing, scrambled data is obtained sequentially in the user data direction Q.
On the other hand, the direction of recording data on a disc is the recording frame direction P and therefore it is necessary to modulate data in the order of the direction P. It is thus required to rearrange the data sequence from the user data direction Q to the recording frame direction P at least before the modulation.
The EDC 505 described above is added to the end of user data, and it is placed at the middle of the user data direction Q in an even number sector. Thus, when transferring the data added with EDC to the recording frame direction P, for example, it is necessary in an even number sector to transfer EDC before all data is completed. However, since the EDC 505 is obtained by performing a predetermined operation on user data of one sector, it is normally impossible to obtain the EDC 505 when there is a lack of user data. Further, in the scrambling process, a scramble value is calculated in the sequence of the user data direction Q on the EDC-added data of each sector. Therefore, in obtaining scrambled data in the sequence of the recording frame direction P, that is, when performing scrambling in the order of the recording frame P, user data is input to the scrambler circuit 101 at a rate of 1 bytes in 216 bytes (once in 216 times). In an odd number sector, the first folded point is at 108th byte.
Accordingly, it is required to perform encoding processing such as EDC addition, scrambling and ECC addition in advance and then transfer data in the recording frame direction. If the user data after the encoding processing such as EDC addition, scrambling and ECC addition is buffered in data buffer in the ascending order of address, transferring data in the recording frame direction requires an access to the addresses of every 216 bytes, for example, thus requiring a data buffer that is capable of random access.
As described above, in Blu-ray disc, it is necessary to transfer data in the recording frame direction P that is different from the user data direction Q along which the EDC creation and the scrambling are performed. This at least requires the process of performing EDC addition and scrambling (path S1) on user data of 1RUB as a recording unit and then reading the data arranged in the user data direction Q in the recording frame direction P (path S2). Since the configuration requires encoding with 2 paths, the data buffer needs to have the capacity of at least 2 clusters, each cluster having 75391 bytes, including EDC and ECC.
Such a data buffer is normally configured by memory. If a data buffer is configured by a memory unit capable of high-speed random access such as SRAM, it allows data supply at high transfer rate in spite of random access; however, it results in significant cost increase, thus being impractical.
On the other hand, if a data buffer is configured by a memory unit that is low cost but unsuitable for high-speed random access such as DRAM, it is unable to make high-speed random access and thus hinders high-speed recording. Configuring a memory with DRAM fails to attain a data transfer rate that allows high-speed recording due to random access, thus being incapable of high-speed recording. Further, though use of a memory capable of burst transfer such as synchronous DRAM (SDRAM) allows high-speed transfer of data to a certain degree for sequential addresses, since data transfer in the recording frame direction P requires high-speed random access, it also fails to achieve high-speed recording.